SCALCORE: DESIGNING A CORE FOR VOLTAGE SCALABILITY Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit Mishra University of Illinois, University of Wisconsin, Nvidia, Intel

Source URL: iacoma.cs.uiuc.edu

SCsafe: Logging Sequential Consistency Violations Continuously and Precisely ⇤ Yuelu Duan, David Koufaty,† and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT

Source URL: iacoma.cs.uiuc.edu

WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication ∗ Sergi Abadal,†‡ Albert Cabellos-Aparicio,‡ Eduard Alarc´on,‡ and Josep Torrellas† † Univ. of Illinois, Urbana-Cham

Source URL: iacoma.cs.uiuc.edu

SCsafe: Logging Sequential Consistency Violations Continuously and Precisely 1 Yuelu Duan, David Koufaty, and Josep Torrellas

Source URL: iacoma.cs.uiuc.edu

Workshop on Advancing Computer Architecture Research (ACAR-II) Laying a New Foundation for IT: Computer Architecture for 2025 and Beyond Organizers: Mark Oskin (University of Washington) and Josep Torrellas (University o

Source URL: cra.org

Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/

Source URL: homes.cs.washington.edu

• Computing
• Microprocessors
• Threads
• Parallel computing
• CPU cache
• Computer memory
• Multithreading
• Microarchitecture
• Threading
• Computer hardware
• Computer architecture
• Central processing unit

Colorama: Architectural Support for Data-Centric Synchronization ∗ Luis Ceze, Pablo Montesinos, Christoph von Praun† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, pmontesi, torrellas}@cs.u

Source URL: homes.cs.washington.edu

• Computer programming
• Critical section
• Lock
• Subroutine
• Linearizability
• Pointer
• Mutual exclusion
• Parallel computing
• Monitor
• Computing
• Concurrency control
• Software engineering

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana

Source URL: homes.cs.washington.edu

• Central processing unit
• Chunk
• CPU cache
• Parallel computing
• C dynamic memory allocation
• Computer memory
• Computing
• Computer hardware

do i: Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas

Source URL: homes.cs.washington.edu

• Central processing unit
• Parallel computing
• Chunk
• Process
• CPU cache
• Computer architecture
• Computing
• Computer hardware
• Computer memory

Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel T. King Gilles Pokam, Cristiano Pereira

Source URL: web.engr.illinois.edu